The present invention relates to an amplifier load circuit which has particular but not exclusive application in an amplifier for adjusting the logic levels used in ECL logic to the logic levels used in CMOS logic.
ECL logic is able to operate at frequencies above 100 MHz and has logic levels of Vdd and (Vdd-400 mV) whereas CMOS logic operates at frequencies below 50 MHz and has logic levels of &gt;(Vdd-500 mV) and &lt;500 mV. Accordingly when providing both types of logic on a single chip and having one pair of power supply lines, say +5 volts and 0V, it is essential to be able to adjust the logic levels of one type of logic to suit the other type of logic. An amplifier is frequently used to adjust the logic levels. Generally the amplifier is of a balanced design with a symmetrical input and output. A criticism of the operation of such an amplifier is that although the output voltages are only slightly delayed with respect to the input signal, there is a poor rise and fall time. This latter effect manifests itself as a smearing of the output signals because they reach their final value only slowly.